By Peter J Cockerell
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Additional info for ARM Assembly Language Programming
As mentioned in chapter two, there are four bits of condition encoded into an instruction word. This allows sixteen possible conditions. If the condition for the current instruction is true, the execution goes ahead. If the condition does not hold, the instruction is ignored and the next one executed. The result flags are altered mainly by the data manipulation instructions. These 1 of 37 ARM Assembly Language Programming - Chapter 3 - The Instruction Set instructions only affect the flags if you explicitly tell them to.
Only word transfers are performed by this group. Branching Although the PC may be altered using the data operations to cause a change in the program counter, the branch instruction provides a convenient way of reaching any part of the 64M byte address space in a single instruction. It causes a displacement to be added to the current value of the PC. The displacement is stored in the instruction itself. SWI This one-instruction group is very important. The abbreviation stands for 'SoftWare Interrupt'.
However, it is possible to store single bytes which may be located at any address. The byte form of STR is obtained by adding B at the end. For example: 24 of 37 ARM Assembly Language Programming - Chapter 3 - The Instruction Set STRB R0,[R1,#1]! will store the least significant byte of R0 at address R1+1 and store this address in R1 (as ! is used). Post-indexed addressing The second addressing mode that STR and LDR use is called post-indexed addressing. In this mode, the
ARM Assembly Language Programming by Peter J Cockerell